This application relates to communications between integrated circuits and particularly to delays applied to digital signals in communication channels between integrated circuits, and to systems and methods for automatically calibrating such delays.
In many situations multiple integrated circuits (ICs) are connected together as part of a larger assembly, for example, on a printed circuit board. Such integrated circuits may be in communication through high-speed communication channels such as provided by parallel communication channels. Examples of such multi-IC arrangements include memory systems where a memory controller may be connected to multiple memory ICs. For example, DRAM, SRAM, and flash memory may be assembled in such multi-IC arrangements.
One type of flash memory that has become particularly popular for mass data storage applications is NAND flash memory. NAND flash memory is cost-effective for mass data storage, where data is not being frequently replaced or updated. For example, USB thumb drives, and Solid State Disks (SSDs) often use NAND flash memory for mass data storage. NAND flash memory chips are generally considered as commodity products that may meet some standardized specifications and communicate through standardized interfaces (e.g. “Legacy” Asynchronous mode and “Toggle Mode” interfaces). In addition to memory cells connected in a NAND configuration, a NAND flash memory chip generally includes peripheral circuits and controller interface circuits that manage communication with a NAND flash memory controller.
A NAND flash memory controller is typically provided within a NAND flash memory system to perform a variety of functions that may include logical-to-physical address translation, Error Correction Coding (ECC), bad-block management, management of multiple NAND flash memory chips, communication with a host system, and other functions. The NAND flash memory controller is located between the NAND flash memory and the host so that the host accesses the NAND flash memory through the controller. A NAND flash memory controller is typically formed as a dedicated chip, an Application Specific Integrated Circuit (ASIC) that is designed to perform the particular functions needed in a particular memory system. Alternatively, some sort of general purpose memory controller may be loaded with firmware that is specific to a particular application. In either case, a NAND flash memory controller chip, separate from the NAND flash memory chip, or chips, is provided and connected between the NAND flash memory and the host.
NAND flash memory systems communicate with host systems over a variety of different interfaces such as USB, Compact Flash (CF), Secure Digital (SD), etc., which allow memory systems to be easily removed from one host and subsequently connected to another host that has an appropriate interface. In contrast, NAND flash memory controller chips and NAND flash memory chips are generally hard-wired to each other (bonded together within the same package, or on the same PCB) and are not configured to be removable. Typically, they are connected together using a simple parallel interface to allow high-speed data transfer. In many cases, a large number of NAND chips are connected to a memory controller to form a large memory such as an SSD. Rapid reliable communication between such integrated circuits is important to overall performance of such an assembly. Skew is one problem that may affect such communication between ICs. One solution to skew may be to reduce clock speeds but this has a negative impact on performance. In some cases, a suitable delay may be used to counteract skew.